This invention relates to cellular trench-gate field-effect transistors, and more particularly to measures for increasing the breakdown voltage of such transistors. The invention also relates to methods of manufacturing such transistors.
Cellular trench-gate field-effect transistors are known, comprising a semiconductor body having an array of transistor cells, in which the cells are bounded by a pattern of trenches lined with dielectric material within the array and around the perimeter of the array. The array trenches extend from a surface of the body through a body region of a first conductivity type into an underlying drain drift region of an opposite second conductivity type. The dielectric material in the array trenches provides a gate dielectric layer adjacent to the body region. A gate electrode on the gate dielectric layer provides a trench-gate in the array trenches, for controlling current flow in a conduction channel from a source region at the surface of the body to the drain drift region in a conductive state of the transistor. A depletion layer is formed in the drain drift region from the p-n junction with the body region and from the trench-gate in a blocking state of the transistor. Premature breakdown of these transistors can occur at high field points in the depletion layer, especially at the perimeter of the array.
It is also known to provide a field plate on the dielectric material in the perimeter trench. Such a transistor with the field-plate connected to its trench-gate is known from the English-language abstract in Patent Abstracts of Japan of JP-A-10214968, the whole contents of which are hereby incorporated herein as reference material. The perimeter trench has an inside wall around the drain drift region of the array and an outside wall on an opposite side of the trench. The perimeter trench is shown as having the same width as the array trenches. The same dielectric layer is shown in the perimeter trench and in the array trenches, so that the field-plate is effectively an extension of the trench-gate. This field relaxation arrangement is adopted to enable a thin gate dielectric to be used without lowering the withstand voltage of the gate.
It is an aim of the present invention to reduce the premature breakdown of cellular trench-gate field-effect transistors that can occur at high field points in the depletion layer, especially at the perimeter of the cellular array.
According to the present invention, there is provided a cellular trench-gate field-effect transistor comprising a field plate on dielectric material in a perimeter trench, characterised in that the dielectric material in the perimeter trench forms a thicker dielectric layer than the gate dielectric layer in the array trenches, and the field plate is present on this thicker dielectric on the inside wall of the perimeter trench without acting on any outside wall. This perimeter field plate is connected to one of the source and trench-gate of the transistor. Furthermore, the array and perimeter trenches are sufficiently closely spaced (and the intermediate areas of the drain drift region are sufficiently lowly doped) that the depletion layer formed in the drain drift region in the blocking state of the transistor depletes the whole of the intermediate areas of the drain drift region between neighbouring trenches at a voltage less than the breakdown voltage.
Thus, the trench-gate trenches and the inwardly-acting field-plate trench are so constructed and arranged in a transistor in accordance with the invention as to reduce the high field points by depleting the areas of the drain drift region between the trenches, without any significant outward extension. This depletion arrangement uses the field-plate and trench-gates in a particular form of the so-called xe2x80x9cRESURFxe2x80x9d technique. Particular advantageous forms of this construction and arrangement can be achieved without requiring extra processing steps in manufacture. In particular, the perimeter trench can be made deeper than the other trenches by making it wider. Due to local loading effects during etching of the array trenches, this increased width can be used to produce automatically a deeper perimeter trench. A thick dielectric used for passivating the trench pattern can be used in the deep trench as the field-plate dielectric. Different dielectric thicknesses can also be advantageously used in the trenches and in different portions of the trenches.
Some of the particularly advantageous technical features and some of the options available with the invention are set out in the appended Claims. These features not only improve the transistor characteristics, but several permit manufacture in a simpler and more cost effective manner. Thus, for example, the perimeter trench may extend to the perimeter of the body, so providing no outside wall and requiring less semiconductor body area. The transistor body region can also extend to the perimeter and so be formed from a non-localised (blanket) dopant implantation and/or diffusion at the body surface or from a doped epitaxial layer.